In a paper published in the journal Communications Physics, researchers reported successful on-chip interfacing of tunable electron and hole quantum dots (QDs) using a 64-channel cryogenic complementary metal-oxide-semiconductor (cryo-CMOS) multiplexer (MUX) with minimal power dissipation. They analyzed charge noise, measured addition energies, and correlated low noise in QDs with sharp transistor turn-on characteristics.
This hybrid quantum-CMOS technology offered a scalable solution for interfacing QDs, allowing for variability analysis and optimization of qubit geometry. The findings marked progress toward building large-scale silicon-based quantum computers.
Study: Scalable on-chip multiplexing of silicon single and double quantum dots. Image Credit: Craig Raymond/Shutterstock.com
Related Work
Past work highlighted the scalability of silicon QDs for quantum computing, demonstrating qubits with improved fidelity and integration with cryogenic electronics. Extending qubit operation to temperatures above 1K and implementing cryo-CMOS multiplexing were identified as key challenges for large-scale systems. The main difficulties were extending qubit operation to "hot" temperatures above 1K and developing low-power cryo-CMOS multiplexing for efficient, large-scale qubit characterization. These hurdles are critical for integrating QDs with classical cryogenic control electronics.
Fabrication and Measurements
The devices were fabricated on 150 mm silicon-on-insulator (SOI) wafers using a customized CMOS process at VTT Technical Research Centre of Finland's (VTT) Micronova cleanroom. The process involved multiple ultra-violet and e-beam lithography layers. The SOI layer was thinned to 35 nm and patterned into nanowires.
A 20 nm SiO2 layer was grown as an insulator between the silicon nanowires and the gate layers, reducing the final Si thickness to 24 nm. The two polycrystalline silicon gate layers were degenerately doped using phosphorous ion implantation, and a thick SiO2 dielectric layer was grown between them. The wafers underwent doping, annealing, and metallization, followed by forming gas anneal passivation.
For the cryo-CMOS design, n— and p-metal-oxide-semiconductor field-effect transistor (MOSFET) transistors were first characterized at room temperature from several test wafers. Transistor modeling and Cadence simulations helped validate the cryogenic-temperature-aware CMOS logic despite needing to fully account for cryogenic transistor characteristics.
The threshold voltages were expected to shift, and the off-current was predicted to be zero at low temperatures. The MUX chip was mounted on a microcontroller board and tested at room temperature using a digital oscilloscope, confirming the selectivity of different devices.
Measurements at 5.6 K were conducted in a cryo-free refrigerator without low-frequency cryogenic filtering, relying on the low-pass cut-off from resistive coaxial cables. Direct current voltages were supplied using commercial digital-to-analog converters, and noise measurements were performed with a lock-in amplifier, voltage dividers, and low-pass filters. Device current was measured with a low-noise transimpedance amplifier and processed through a spectrum analyzer. This setup allowed for precise noise and current measurements across various frequencies.
Further measurements at 2.5 K and 300 mK were performed using a cryo-free version of Oxford Instrument's Heliox, equipped with cryogenic low-pass filtering. The same equipment was used for voltage and current measurements. An ambipolar transistor was measured at 3.5 K using a cryogenic probe station and a parameter analyzer, providing a noise floor of approximately 10 nA.
Cryogenic CMOS MUX Integration
The research presented a chip integrating cryogenic CMOS MUX and QD devices showcased through various micrographs. The MUX comprises a 6-to-64 decoder and analog switches formed by n- and p-MOSFETs, enabling the selection of 64 devices, including electron and hole quantum dots. Device selectivity was confirmed, with leakage currents below 1 picoampere (pA) and power dissipation under 1 pW. Measurements indicated low subthreshold swing values of 4 mV/Dec at 5.6 K, indicating low disorder in the MOSFET channels. The CMOS logic operated effectively at cryogenic temperatures, demonstrating tunability and potential for analog applications.
Charge noise in silicon spin qubits is a critical factor limiting qubit performance. It affects spin coherence through mechanisms such as spin-orbit coupling, notably weaker in silicon than in III-V materials. Despite silicon's relatively weak spin-orbit coupling, its impact on the spin coherence of silicon QDs is significant, especially for hole Si spin qubits, which have stronger coupling.
Integrating silicon spin qubits with on-chip cryo-CMOS electronics for operation above 1 K is essential for practical quantum computing, although increased temperature correlates with heightened charge noise. The study analyzed low-frequency charge noise across various Coulomb peaks in quantum dots, revealing that charge noise diminishes as more electrons are added to the quantum dot due to partial screening of charge traps. Moreover, while the observed threshold voltage variability in QDs aligns closely with adjacent MOSFETs, electron and hole QDs exhibited consistent threshold voltages, affirming their fabrication quality and operational effectiveness at cryogenic temperatures.
Conclusion
To sum up, the study demonstrated a hybrid quantum-dot-CMOS circuit, integrating a cryogenic MUX with electron and hole QD, exhibiting low charge noise at 5.6 K. It correlated low charge noise with minimal subthreshold swings in n- and p-MOSFETs, indicating low disorder in the silicon channel.
The research highlighted the potential of the CMOS process for spin qubits and emphasized the advantages of integrating this technology with other cryogenic devices to enhance quantum computing capabilities. It also noted the ongoing debate regarding the superiority of electron versus hole spin qubits for large-scale silicon quantum computing.
Journal Reference
Heorhii Bohuslavskyi, Ronzani, A., et al. (2024). Scalable on-chip multiplexing of silicon single and double quantum dots. Communications Physics, 7:1. DOI:10.1038/s42005-024-01806-3, https://www.nature.com/articles/s42005-024-01806-3
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