In a paper published in the journal Communications Physics, researchers have achieved a significant milestone in quantum computing technology by successfully interfacing tunable electron and hole quantum dots (QDs) with a 64-channel cryogenic complementary metal-oxide-semiconductor (cryo-CMOS) multiplexer (MUX) on a single chip.
Study: Scalable on-chip multiplexing of silicon single and double quantum dots. Image Credit: Craig Raymond/Shutterstock.com
This hybrid quantum-CMOS technology offered a scalable solution for interfacing QDs, allowing for variability analysis and optimization of qubit geometry. The findings marked progress toward building large-scale silicon-based quantum computers.
Related Work
Previous research has highlighted the scalability of silicon QDs for quantum computing, demonstrating qubits with improved fidelity and integration with cryogenic electronics. Key challenges identified include extending qubit operation to temperatures above 1K and developing low-power cryo-CMOS multiplexing for efficient large-scale qubit characterization. These hurdles are critical for integrating QDs with classical cryogenic control electronics, making advancements in these areas essential for practical applications.
Device Fabrication
The devices were fabricated on 150 mm silicon-on-insulator (SOI) wafers using a customized CMOS process at VTT Technical Research Centre of Finland's Micronova cleanroom. The fabrication process involved multiple ultra-violet and e-beam lithography layers. The SOI layer was thinned to 35 nm and patterned into nanowires. A 20 nm SiO2 insulator layer was grown, reducing the final silicon thickness to 24 nm.
Two polycrystalline silicon gate layers were deposited and degenerately doped using phosphorus ion implantation. A thick SiO2 dielectric layer was grown between the gate layers. The wafers underwent subsequent processes of doping, annealing, metallization, and forming gas anneal passivation to complete the fabrication.
Cryo-CMOS Design and Characterization
For the cryo-CMOS design, n- and p-MOSFETs were first characterized at room temperature from several test wafers. Transistor modeling and Cadence simulations were employed to validate the cryogenic-temperature-aware CMOS logic, despite not fully accounting for cryogenic transistor characteristics. The threshold voltages were expected to shift, and the off-current was predicted to be zero at low temperatures. To confirm functionality, the MUX chip was mounted on a microcontroller board and tested at room temperature using a digital oscilloscope, which verified the selectivity of different devices.
Cryogenic Measurements
Measurements at 5.6 K were conducted in a cryo-free refrigerator without low-frequency cryogenic filtering, relying on the low-pass cut-off from resistive coaxial cables. Direct current voltages were supplied using commercial digital-to-analog converters. Noise measurements were performed with a lock-in amplifier, voltage dividers, and low-pass filters. Device current was measured with a low-noise transimpedance amplifier and processed through a spectrum analyzer, allowing for precise noise and current measurements across various frequencies.
Further measurements at 2.5 K and 300 mK were performed using a cryo-free version of Oxford Instrument's Heliox, equipped with cryogenic low-pass filtering. The same equipment was used for voltage and current measurements as in the 5.6 K setup, ensuring consistency in the measurement approach.
An additional measurement of an ambipolar transistor was conducted at 3.5 K using a cryogenic probe station and a parameter analyzer. This setup provided a noise floor of approximately 10 nA, demonstrating the high sensitivity of the measurement system.
Cryogenic CMOS MUX Integration
The research presented a chip that integrates cryogenic CMOS MUX with QD devices. This integration was demonstrated through various micrographs, showcasing the potential for advanced quantum computing applications.
The MUX comprised a 6-to-64 decoder and analog switches formed by n- and p-MOSFETs, enabling the selection of 64 devices, including both electron and hole quantum dots. Device selectivity was confirmed, with leakage currents below 1 picoampere (pA) and power dissipation under 1 pW. Measurements indicated low subthreshold swing values of 4 mV/Dec at 5.6 K, suggesting low disorder in MOSFET channels. These results demonstrate the effective operation of CMOS logic at cryogenic temperatures, highlighting its tunability and potential for analog applications.
Charge noise is a critical factor limiting qubit performance in silicon spin qubits. Its impact on spin coherence is significant despite silicon's relatively weak spin-orbit coupling compared to III-V materials. This effect is particularly pronounced in hole Si spin qubits, which exhibit stronger coupling. Integrating silicon spin qubits with on-chip cryo-CMOS electronics for operation above 1 K is essential for practical quantum computing. However, increased temperature correlates with heightened charge noise.
The study's analysis of low-frequency charge noise across various Coulomb peaks in quantum dots revealed that charge noise diminishes as more electrons are added to the quantum dot due to partial screening of charge traps. Moreover, while the observed threshold voltage variability in QDs aligns closely with adjacent MOSFETs, electron and hole QDs exhibited consistent threshold voltages. These findings affirm the fabrication quality and operational effectiveness of the integrated devices at cryogenic temperatures, marking a significant step forward in the development of practical quantum computing systems.
Conclusion
This study demonstrated a hybrid quantum-dot-CMOS circuit that integrates a cryogenic multiplexer (MUX) with both electron and hole quantum dots (QDs), achieving low charge noise at 5.6 K. The correlation between low charge noise and minimal subthreshold swings in n- and p-MOSFETs indicates low disorder in the silicon channel.
The research highlights the potential of CMOS technology for spin qubits and emphasizes the benefits of integrating it with other cryogenic devices to enhance quantum computing capabilities. Additionally, it contributes to the ongoing discussion about the advantages of electron versus hole spin qubits for large-scale silicon quantum computing. Overall, this work advances our understanding of hybrid quantum-classical systems and moves us closer to practical, scalable quantum computers.
Journal Reference
Heorhii Bohuslavskyi, Ronzani, A., et al. (2024). Scalable on-chip multiplexing of silicon single and double quantum dots. Communications Physics, 7:1. DOI:10.1038/s42005-024-01806-3, https://www.nature.com/articles/s42005-024-01806-3
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