A paper recently published in the journal Scientific Reports has proposed the use of machine learning for cross-architecture tuning of silicon-germanium (SiGe) and silicon (Si)-based devices.
Gate-voltage space exploration. Different charge carriers (gate operation modes) are represented in different columns (rows). Each panel illustrates the initial placement of the origin (white circle), search boundary (red cross), and search direction (black arrow). The gate voltage space is divided into regions of near-zero (blue) and non-zero (pink) current. Regions of voltage space that cannot be explored due to the gate voltage bounds set to avoid device damage are greyed out. Image Credit: https://www.nature.com/articles/s41598-024-67787-z
Tuning Challenges and Machine Learning
The potential of SiGe and Si-based devices for scaling quantum circuits is currently limited by device variability. Each device requires individual tuning to meet operational conditions, necessitating a unique protocol for every instance. Despite this challenge, SiGe and Si devices offer significant advantages for encoding spin qubits, including long coherence times, high fidelities, and a path to scalability.
Gate-defined quantum dots in SiGe and Si are particularly promising for constructing circuits with a large number of qubits, which is crucial for achieving a universal fault-tolerant quantum computer. These devices are tuned using multiple gate electrodes to ensure they operate within similar regimes.
However, the parameter space for each device's material realization and architecture is unique. This makes tuning semiconductor devices a time-consuming and complex task, especially when integrating various architectures to build intricate quantum circuits with millions of components. For example, tuning a double quantum dot device can take over 3 hours of expert time.
Automating this tuning process through machine learning is extremely challenging. Although several algorithms address parts of the tuning problem, only a few have been validated across different device architectures and offer meaningful insights into the parameter space. Furthermore, no existing algorithm has been tested on material compositions suitable for large-scale scalability.
The Study
In this work, the researchers introduced a machine learning-based algorithm called Cross-Architecture Tuning Solution using Artificial Intelligence (CATSAI) for automatically tuning quantum dots across three different material systems and device architectures: a 7-gate Ge/SiGe heterostructure double quantum dot device, a 5-gate GeSi nanowire, and a 4-gate Si FinFET.
CATSAI requires specific hyperparameters to be set in a configuration file for each device type. These include the Coulomb peak segmentation threshold, the offset current noise floor, the size and resolution of acquisition current traces and maps, safety voltage bounds, and source-drain bias. The algorithm also allows for arbitrary selection of gate and origin voltage sweep directions, accommodating devices with depletion or accumulation mode gate electrodes and either electrons or holes as the majority charge carriers. Advanced signal-processing methods handle charge switches and noise patterns.
CATSAI Workflow:
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Initialization Stage: The bias voltage is fixed, and current measurements are taken with all gate electrodes set to their maximum permissible value and to 0 V. This stage determines the current range.
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Sampling Stage: The algorithm selects a vector of gate voltages for tuning based on a Gaussian process model of the hypersurface and weighting from the Coulomb peak finding probability. This vector represents all gate voltages considered for tuning. The algorithm also identifies the pinch-off onset as a current drop below a specific threshold. The N-dimensional hypersurface is defined by the pinch-off voltages of the N gate electrodes for each device.
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Investigation Stage: A high-resolution current trace is performed once the pinch-off is aligned with a specified gate voltage direction. The current trace is recorded with a resolution of 0.78 mV/pixel for the heterostructure and FinFET devices, and 1.56 mV/pixel for the nanowire, with a fixed length of 128 pixels. The presence of Coulomb peaks in the current trace is determined using a random forest classifier, which is crucial to CATSAI’s success across different device types with varying noise characteristics.
The configuration file sets the direction, origin, and bounds for gate-voltage space exploration, ensuring that CATSAI can be adapted for different charge carriers and accumulation/depletion modes of the gate electrodes.
Significance of the Study
In this study, the researchers successfully demonstrated fully automated quantum device tuning across various gate architectures and material compositions using the CATSAI algorithm. The algorithm achieved rapid tuning times for all three device architectures tested: 92 minutes for the Ge/SiGe heterostructure device, 10 minutes for the GeSi nanowire, and 30 minutes for the Si FinFET.
CATSAI notably reduced tuning times compared to the random search algorithm, which took 17 minutes for the GeSi nanowire and 360 minutes for the Ge/SiGe heterostructures. This highlights CATSAI’s efficiency and its general applicability for different devices.
Additionally, CATSAI provided valuable insights into the parameter space landscape for each device, allowing for detailed characterization of regions with double quantum dot regimes. This automated tuning capability is a significant step towards semiconductor qubit scaling.
In summary, this study illustrates that machine learning can offer comprehensive solutions for the tuning of quantum devices, opening the door to more scalable and efficient quantum computing technologies.
Journal Reference
Severin, B. et al. (2024). Cross-architecture tuning of silicon and SiGe-based quantum devices using machine learning. Scientific Reports, 14(1), 1-10. DOI: 10.1038/s41598-024-67787-z, https://www.nature.com/articles/s41598-024-67787-z
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